Reducing DRAM’s power footprint has always been table stakes for vendors like Micron Technology, but AI-driven data centers are putting more pressure on memory makers to make further advances in power efficiency.
Micron recently announced it is shipping samples of its 1γ (1-gamma), sixth-generation (10 nm-class) DRAM node-based DDR5 memory. The 16Gb DDR5 memory is designed to offer speed capabilities of up to 9200MT/s, a 15% speed increase compared to its predecessor, while also reducing power consumption by 20% by using next-generation high-K metal gate CMOS technology paired with design optimizations.
In a briefing with EE Times, Praveen Vaidyanathan, Micron’s VP of DRAM process integration, said Micron’s sixth generation of what the company is calling its “one series” is driving performance, power, bit density and capacity improvements with each successive node. He said increasing performance is always a top priority with each new node, but power reduction was a big focus for 1-gamma.
These power improvements have been incremental since Micron went from 1-z to 1-alpha, Vaidyanathan said, with goal of achieving double digit power reduction with every technology node. “Trying to drive reduced power consumption from memory was a key focus and we were able to deliver more than 20% improvement on any product that’s built with 1-gamme compared to 1-beta,” he said.
He added that this milestone is especially important for data centers, which have become more memory centric in the AI era, but PC and client platforms also benefit. “Today, we expect the initial advantage to really be on the server and data center platforms.”
Vaidyanathan said the JEDEC DDR5 standards provide a baseline for Micron to improve upon with its own designs—especially when customers want the lowest power consumption possible.
The design of Micron’s 1-gamma has benefited from successfully integrating EUV lithography along with the company’s advanced multi-patterning techniques to achieve a 30% increase in bit density. High-K metal gate CMOS technology, meanwhile, enables better transistor performance.
In an interview with EE Times, Jim Handy, principal analyst with Objective Analysis, noted that Micron is the last of the “Big Three” DRAM makers to move to EUV. “The company has a longstanding reputation as one that uses older processing equipment longer than anyone else by adopting other clever innovations,” Handy said.
Micron was the first to use self-aligned double-patterning in the early 2000s as a means to delay the purchase of expensive immersion scanners, he added, and did the same with EUV imagers, which cost more than $100 million each.
Handy said the industry is now in the six-generation named “1-something processes,” which gives the general impression that very little progress is now being made in die shrinks. “The details that Micron has released with this announcement make it clear that progress is still moving at a good pace, despite the industry’s cryptic process node nomenclature,” he said.
Handy also noted that Micron said there are more than 30% more bits per wafer with 1-gamma than with 1-beta, and likewise with 1-beta compared to 1-alpha, and 1-alpha compared with 1-z. “That brings us to a total of over 220%, or more than twice as many bits per wafer on 1-gamma as on 1-z to continue to drive costs down,” he said.
Micron’s 1-gamma node will first be used for its 16 Gb DDR5 DRAM and over time will be integrated across the company’s memory portfolio.
Vaidyanathan said Micron’s 1-gamma samples are going out to the company’s CPU partners and select customers over the next one to two quarters as part of its technology enable program to support interoperability and qualification work across multiple platforms and segments. “We believe this has become an integral part of how you successfully launch new technologies and new products,” he said.
From EETimes