At SEMICON Europa this week, Applied Materials and BE Semiconductor Industries (BESI) gathered a small group of journalists for a press briefing on what the companies describe as the industry’s first high-volume–ready die-to-wafer hybrid bonding platform. The partners spent five years developing the integrated Kinex system, which is now being adopted in production by logic, memory and OSAT customers.

Hybrid bonding has been discussed for years as a way to break through scaling limits. What is striking, according to the two speakers, is how rapidly demand is accelerating—and how much engineering complexity is still involved.

Increasing interest in hybrid bonding

“Moore’s Law is slowing,” said Chris Scanlan, senior VP of technology at BESI. “Transistor density is still increasing, but at a slower rate. And at the same time, designers are hitting the reticle-size limit. For many high-performance chips, you simply have to split the die and put it back together using advanced packaging.”

That is the essence of the chiplet trend. Instead of a monolithic SoC on the most advanced process node, designers now mix dies from different nodes and stitch them together at extremely fine pitches. But as Scanlan emphasized, “once you split the die, you need an interconnect technology with very high density, very low loss, and very tight pitch. That technology is hybrid bonding.”

Hybrid bonding joins dies or wafers through direct dielectric-to-dielectric and copper-to-copper interfaces. That eliminates solder bumps and the organic dielectric layers that limit performance and power efficiency.

Gaurav Mehta, director of product marketing for Kinex at Applied Materials, highlighted the drivers. “We’re expecting to see future package sizes expand by 9× and silicon areas increase by 600× in next-generation AI accelerators,” he said. “Some of these packages will have more than 400 dies. Achieving the required bandwidth and latency means shrinking the interconnect gap and packing in more I/Os—upwards of a million I/Os per square millimeter. Hybrid bonding is what enables that.”

Compared to micro-bumps, hybrid bonding reduces thermal resistance, lowers power, cuts latency and shrinks footprint. Applied Materials said the efficiency gains can reach 10× on certain architectures. But despite its promise, the technology is not fully mature. “It’s fair to say this is not a mature technology yet,” Mehta acknowledged. “It still is in its ramp stages. But there are products that have been running in high volume for two or three years, and adoption is increasing.”

Wafer-to-wafer hybrid bonding has been used for close to a decade in memory and image sensors, where die sizes match. “Wafer-to-wafer works when your dies are the same size and your yields line up,” Mehta explained. “But for chiplets, where you may have five different functions, different nodes, and different die sizes, wafer-to-wafer is not practical. Die-to-wafer lets you bond different chiplets coming from different nodes in one planar bonding step.”

This is why die-to-wafer is the key to multi-chiplet packages used in GPUs, CPUs, AI accelerators and upcoming glass-substrate–based modules. And because every incoming die has its own bin, speed grade and quality level, die-level flexibility is essential.

A fully integrated hybrid bonding line

What Applied Materials and BESI said they built together is an integrated line covering every step of the die-to-wafer hybrid bonding flow: surface preparation, plasma activation, cleaning, metrology, alignment and bonding. “This is the first high-volume die-to-wafer hybrid bonding system,” Scanlan said. “It’s a very compact machine, but extremely sophisticated.”

He explained the sequence: Dies arrive on a film frame, already singulated. The target wafer and component wafer are loaded through separate ports. The system uses a multi-stage metrology and vision stack to determine the position of each die, measure alignment to fiducials and correct placement before contact.

“We have to achieve 100-nm alignment, at three sigma,” Scanlan said. “And once the die touches the wafer, Van der Waals forces lock it in. There’s no self-alignment like in flip-chip. So, we have to be extremely precise in the initial placement.”

With today’s Kinex system, customers are achieving 1,600 die placements per hour in high-volume production—up to 2,000 depending on process, according to Scanlan. The platform is scalable: up to six bonder modules can be integrated.

The companies stressed that the single-wafer integrated flow is a key differentiator. Batch surface-prep systems create long “queue times,” where wafers sit after activation, waiting for bonding—and surfaces degrade. In a standalone factory configuration, this queue can reach 13 hours.

“Kinex shortens the readiness window to minutes,” Mehta said. “The system prepares material only when the bonder is ready. If you prepare surfaces too early, you get yield loss and contamination issues. With Kinex, queue-time degradation is cut by roughly 10×.”

Another advantage: eliminating fab-floor moves. Instead of shuttling wafers among multiple tools—clean, plasma, bond, metrology—the entire process stays within a class-one enclosure. Mehta said customers see significantly lower particle-related defects and higher yields as a result.

Customers also increasingly want automated die-bin matching—not all chiplets in a module will come from “bin 1.” Kinex ingests wafer maps and matches dies according to customer-specified rules, reducing manual engineering overhead and scrap, according to the speakers.

Why customization matters

Hybrid bonding is drawing intense interest, Scanlan said, pointing out that the supply side is reacting. “Everybody is developing a hybrid bonder. Japanese players, Korean players, Chinese players, European players—all of them.”

But he argued that Applied and BESI hold an advantage through their joint Center of Excellence (COE) in Singapore. “We get the first look at many of these new applications,” he said. “Customers want to do evaluations and engineering builds, and we can support all of that. We’ve been expanding our COE so we can co-optimize not just the bonding step but what comes before and after.”

The COE includes a range of tools for process co-optimization, allowing customers to tune the entire flow, including warpage engineering. “Warped incoming material is a reality,” Scanlan said. “We know how to manage it on the bonder, but we also work with customers on wafer-level warpage engineering.”

The next-generation hybrid bonder will launch in 2026 with notable improvements, according to Scanlan. “With this upgrade, we’re trying to achieve 50-nm accuracy or better,” he said. “That allows finer pitches for higher-bandwidth chip-to-chip connections. And at the same time, we’re increasing throughput.”

Memory customers—who bond 16-20 dies per package—prioritize throughput more than pitch, and the new architecture lets them trade accuracy for speed. A more radical architectural redesign is already underway for the generation after that, pushing below 25-nm alignment accuracy while increasing unit-per-hour rates further. “We have to do both—improve accuracy and improve productivity,” Scanlan said. “This is our roadmap.”

As both speakers emphasized, hybrid bonding is not yet “plug-and-play.” Yields vary, surfaces are hypersensitive to contamination and metrology requirements keep climbing. But the trajectory is clear. The shift from monolithic SoCs to multi-chiplet architecture is accelerating. AI workloads are pushing package sizes and I/O counts to unprecedented scales. And the economics of mixing process nodes is too powerful to ignore.

The Applied–BESI Kinex system is marketed as one of the first hybrid bonding platforms proven in high-volume production, and both companies are now racing to extend its accuracy, speed and flexibility.

“Hybrid bonding is becoming a go-to technology,” Mehta said. “The application space is diverse, and we’re just at the beginning.”

From EEtimes