Static random-access memory (SRAM) has become such a well-established memory that it is now perceived as off-the-shelf “plumbing,” but Marvell Technology’s latest custom SRAM aims to demonstrate how the incumbent memory has a role to play in artificial-intelligence data centers.

Claiming it to be the industry’s first 2-nm custom SRAM, Marvell said it is designed to enhance memory hierarchy performance within accelerated infrastructure and boost the performance of custom XPUs and devices powering cloud data centers and AI clusters by delivering up to 6 Gb of high-speed memory. It also significantly reduces memory power consumption and die area at comparable densities, the company said.

Marvell’s SRAM consumes up to 66% less power than standard on-chip SRAM at equivalent densities, while operating at up to 3.75 GHz. Power has become a critical metric for AI clusters and data centers looking to manage their energy footprint and effectively cool components.

In a briefing with EE Times, Darren Anand, Marvell’s lead memory architect, said the company has been focusing a lot on optimizing SRAM for AI and machine-learning applications. “We have a lot of synergy with some of the packaging and custom HBM work that we’re doing where we can open up more die area on the XPU for compute.”

Anand said Marvell’s SRAM can keep some workloads on-die rather than always going to the HBM and support the high bandwidth and wide I/O demanded by AI workloads. “That can help the overall device performance.”

SRAM is the only viable high-performance memory that can support a near-memory compute architecture, as it’s the only one available at the single-digit nanometer process nodes, Anand said. “Those advanced nodes don’t offer DRAM on the same piece of silicon.” Similarly, NAND flash and emerging memories such as MRAM, ReRAM, or PCM aren’t available at advanced nodes either, he added.

SRAM can be embedded on the same die as the logic at advanced nodes to support memory hierarchy layers that are immediately available to the processor, the processing, and logic engines on the XPUs, unlike a standard von Neumann architecture that connects memory with the processing logic, Anand said. A near-memory compute architecture puts the data closer to where it needs to be, reducing the power required to move it while increasing bandwidth.

Anand said that in a typical XPU, at least 30% of the silicon area is dedicated to SRAM, and on some designs, it’s more than 50% or 60% of the die. “We’re trying to optimize that because we can really move the needle in terms of chip die size and cost,” he added.

Anand said the industry view of SRAM is that it’s become the plumbing equivalent of foundational IP: It’s needed in a lot of places, but there’s no innovation around the technology. “The reality is that there’s a lot of novelty that can be implemented in the SRAM architecture,” he said. Power, bandwidth, or whatever other metrics matter can be optimized, he added. “We don’t look at it as just plumbing; we look at it as an opportunity for innovation.”

The primary challenge for SRAM has been area scaling, Anand said. Historically, both the logic and the memories span generation to generation. “They’ve kind of started to hit a wall on the SRAM cell, where the scaling over the last few advanced nodes has started to flatten off,” he said. “The logic has continued to scale, but the memory bit cells are not.”

Jim Handy, principal analyst with Objective Analysis, said there are power savings and additional speed in Marvell’s approach while accommodating the fact that the SRAM chip isn’t shrinking in proportion with process. “They’ve made the SRAM shrink a little bit for those process geometries,” he said.

Handy said SRAM has been widely used for cache memories on advanced processor chips. “If the chip doesn’t have to go off-chip to use a memory, then it can go way faster,” he said. “It can actually perform one instruction per cycle for every single core that’s in the chip, and that’s just really fast.”

From EETimes