FlexGen, a network-on-chip (NoC) interconnect IP, is aiming to accelerate SoC creation by leveraging AI.

Developed by Arteris Inc., FlexGen promises to deliver a 10× productivity boost while reducing design iterations and the time required to develop. In a briefing with EE Times, Arteris CMO Michal Siwinski said FlexGen achieves up to a 30% reduction in wire length to lower power use, as well as up to 10% reduction in latency that results in improved performance in SoC and chiplet designs.

“It will actually do the process of generating that network on chip, generating that interconnect and it will actually generate however many interconnects are required to meet the requirement,” Siwinski said.

Using AI and machine learning for chip design isn’t new, Siwinski said, but often the productivity boosts come at the cost of performance or power. FlexGen is able to reduce the number of elements on the critical path of a project, while also improving power/performance metrics, which he said is unique.

FlexGen is based on Arteris’ FlexNoC 5 IP technology and component library and supports SoC and chiplet design automation based on Arm, RISC-V and x86 processors. Andy Nightingale, VP of product management and marketing at Arteris, said AI enables the company to reduce manual adjustments by more than 90%, which means optimized NoC topologies can be generated in hours instead of days.

He said these advancements are necessary as the industry scales to meet the demands of advanced technologies like AI, as well as autonomous driving and cloud computing, which have led to larger, more complex designs—typical traditional best-in-class manual approaches are no longer sufficient.

Nightingale said the industry has reached the point where manual NoC generation is beyond human capability, which is why AI and machine learning is needed to meet the complex designs that are being by driven by AI. Arteris quickly considered all the properties and requirements of all the IP blocks that were being connected to do develop the NoC generation, he said. “That gives a massive productivity boost compared to manual efforts.”

One example of a customer that is benefiting from FlexGen is Dream Chip Technologies, which specializes in automotive AI used for advanced driver assistance systems (ADAS). FlexGen has enabled the company to create floorplan adaptive topologies with complex automotive traffic requirements within minutes.

Nightingale said productivity and speed of design are not the only benefits for customers but also reduced wire lengths. “The overall wire length of the system-on-chip has a big impact on the power of the design.”

Nightingale added that AI-enabled design tools and automation are critical for the semiconductor industry as there is a huge shortage of expertise. Using a tool like FlexGen also gives designers more time to explore and experiment to improve designs, he said, and the more complex the design, whether it is for an AV or AI data center, the more designers can benefit from using FlexGen. “The more complex the design, the better the results are going to be.”

FlexGen is just one of many examples of how AI is being used to boost productivity in semiconductor design. Digital twins have recently begun to take advantage of more sophisticated AI models, which allows them to be more accurate and allow for more experimentation. AI supports the development of foundation models that are relatively generic and can be added to with domain-specific and proprietary information.

The recent increase in chiplet adoption, meanwhile, has led to the growing need to accelerate analysis, design and deployment. Baya Systems’ algorithm-driven system architecture platform, WeaverPro, combined with its scalable IP and cache fabric, Weave IP, pulls together all the steps of building out chiplet architectures through data-driven design and optimization.

More recently, an update to the Arm Total Design initiative focuses on expanding the chiplet ecosystem with the launch of an AI/CPU chiplet platform that targets the cloud, high-performance computing and AI/ML training and inference workloads.

From EETimes