A recent standard update by the JEDEC Solid State Technology Association is enhancing the security and reliability of DDR5 SDRAM, while Rambus has added power management capabilities to DDR5 DIMMs.

Security and power management at the memory-device level has become increasingly important with the growth of AI workloads as models and proprietary algorithms represent highly valuable IP and AI-driven data centers threaten to drive up power consumption.

The JESD79-5C DDR5 SDRAM standard introduces per-row activation counting (PRAC) to improve DRAM data integrity to enhance performance in a wide range of applications, from high-performance servers to emerging technologies like AI and machine learning, as well as improve security. PRAC precisely counts DRAM activations on a worldline granularity, so when the DRAM detects an excessive number of activations, it alerts the system to pause traffic and to designate time for mitigative measures.

In a briefing with EE Times, JEDEC JC-42 committee chair Christopher Cox said the standards reflect how security is a fundamental cornerstone of DRAM design, whether it is DDR, LPDDR, GDDR or HBM. “We have to keep it secure.”

But threats are constantly evolving, so as soon as vulnerabilities are discovered they must be addressed in the appropriate memory standard, he said. “As you can imagine with silicon, it takes a little bit longer to do that.”

Cox said security is table stakes along with power and performance requirements. With DDR5, there were additional mitigations for security threats like RowHammer as part of an effort to harden DRAM against vulnerabilities. PRAC functionality is an extension of those capabilities, which is adding counters on every single row inside of the DRAM—there can be thousands of rows, he said. “Now we have micro counters for every one of these rows, so we can watch for misbehaving activity where somebody’s trying to activate that device too much and it’s outside of just normal read access.”

When a row is getting hammered, it is activating repeatedly and suspiciously trying to activate its sibling rows, which is when bit flips occur. A write-only device is not very useful, Cox said, but PRAC provides the ability to watch for suspicious activity while adding mechanisms that allow the DRAM to let the host know when there is an issue by setting a threshold.

Adding features like PRAC always come with a performance price, Cox said, whether it is error correction, detecting malicious activity or mitigating against natural bit failures. “Everything comes with a cost, whether it’s die size impact or an actual performance impact.”

Ideally, you want to keep the DRAM simple and add the complexity to the controller, he said, but RowHammer is an example of when the cell design is being used against itself.

DRAM has evolved to become more than a simple device that is read and written to—it is part of a complex systems that must balance security, performance and power management. The latter is something Rambus is addressing with a new family of DDR5 server power management ICs (PMICs).

Rambus’ PMIC is designed to enable more memory channels, higher capacity modules and greater bandwidth, as well as includes products for the JEDEC extreme current (PMIC5020), high current (PMIC5000) and low current (PMIC5010) specifications.

Just as JEDEC has intentionally looked to bolster security in DDR5, a conscious effort to address power management on DIMM began about five years ago, John Eble, executive VP of product marketing at Rambus, said in interview with EE Times.

In previous DDR generations, power was regulated on the motherboard, and it had to deliver a low voltage at high current across the motherboard through a connector and then onto the DIMM. Because supply voltages have been reduced over time to maintain power levels at higher data rates, maintaining the desired voltage level became increasingly challenging due to IR drop, which is the voltage drop that occurs when current flows through a resistor.

Implementing a PMIC on the DDR5 RDIMM all but eliminates IR drop, Eble said, as data centers are trending toward delivering as high voltage as possible to get as close to the end point of usage as possible. He said the DDR5 DIMM is able to step down the voltage to what ever is required, which provides flexibility on the DIMM to hit performance targets—all while ensuring power integrity.

Adding power management and security features to DDR5 DIMMs is ultimately possible because of a smarter DIMM architecture that helps to meet the industry’s goal for increased memory bandwidth and capacity while maintaining power within the same envelope on a per-module basis. Eble said it is more economical for customers to add power management as they add DIMMs.

Rambus has also been tackling security challenges for DRAM, including RowHammer. Its Row Address Map Permutation and Reassignment Technique (RAMPART) mitigates RowHammer attacks and improves server memory system reliability by remapping addresses in each DRAM. The novel approach, which is compatible with DDR5’s RowHammer mitigation features, confines RowHammer bit flips to a single device for any victim row address.

When paired with today’s error detection and correction methods, a system employing RAMPART can detect and correct bit flips from a successful attack, allowing the memory system to heal itself.

 ----Form EE Times